1. Field of the Invention
The present invention relates to an fabrication of an integrated circuit structure. More particularly, the present invention relates to a method for fabricating an interconnect structure.
2. Description of the Related Art
With the rapid development in the IC industry, the integration degree of semiconductor devices is always required higher so that the IC process linewidth is decreased unceasingly. Hence, the process window of a back-end interconnect process is decreased rapidly, especially when a via/contact hole is to be formed. This is due to the high aspect ratio of the via/contact hole, and results in quite a few problems.
FIG. 1 illustrates a cross-sectional view of a conventional contact plug of MOS transistor. The contact plug 150 is disposed between two MOS transistors 110 and 120 electrically connecting with a shared source/drain (S/D) region 130, wherein the MOS transistors 110 and 120 are covered by a dielectric layer 140 in which the contact plug 150 is formed. When the process linewidth is reduced, the contact hole 145 is shrunk but the dielectric layer 140 cannot be thinned correspondingly, so that the aspect ratio of the contact hole 145 is raised. Consequently, some dielectric material easily remains at the bottom of the contact hole 145 to cause a high contact resistance or even an open circuit and a void defect easily forms in the subsequent conductor gap-filling process, so that the reliability of the device and the yield of the product are lowered.